1. Field of the Invention
The present invention relates to a phase changing circuit in a logic circuit which includes an emitter-coupled logic (ECL) circuit having a plurality of emitter output circuits.
2. Description of the Related Art
In a clock synchronizing type data processor, clock signals having desired phases must be distributed to latches in the processor. Usually, the desired clock signals are obtained by making use, in a clock distribution circuit, of a delay line with delay value adjustable by taps or discrete wires (pair wires, fine wires, coaxial cables, etc.) with delay values adjustable by changing the length.
However, when data processors are formed by large-scale integrated circuits (LSI) of high densities, there is insufficient space for the delay lines or the discrete lines. Therefore, a circuit for adjusting (changing) the phase by a gate in an LSI is desired.